IEEE 1394-1995 decoders are based on a non return to zero (NRZ) transmission of data signal in which a strobe is also transmitted to recover the digital data from the NRZ data signal. From the NRZ data signal and the strobe, a recovery clock may be constructed which is used to extract the actual digital data from the NRZ data signal. The transmission of NRZ data signal and the strobe allows for a reliable transmission and receipt of digital data. During packet transmission, there is only a single node transmitting on the bus, so the entire media can operate in a half duplex mode using the two signals: Data and Strobe. As shown in FIG. 1, NRZ data is transmitted on Data and is accompanied by the Strobe signal which changes state whenever two consecutive NRZ data bits are the same, ensuring that a transition occurs on either Data or Strobe for each data bit. FIG. 2 illustrates an example of an IEEE 1394-1995 decoder 5. Decoder 5 receives the NRZ data signal and the strobe to generate a recovery clock using a plurality of flip flops 10, 15, and 20 to generate data data_1, data data_0 and a quarter clock qrt_clk, respectively. The three signals are then used to construct the original digital data transmitted by the source. A clock that transitions each bit period can be derived from the exclusive—or of Data with Strobe. The primary rationale for use of this transmission code is to improve the skew tolerance of information to be transferred across the serial bus.
However, the generated signals from the decoder are not useful because the recovered data and the recovered clock need to be in sync with the local clock of the circuit using the data. Generally, this function is performed by a data re-timing circuit. Previously, a phase locked loop (PLL) circuit was used for timing and carrier recovery to ensure optimal data sampling using a local clock. However, there are many disadvantages to using a PLL based circuit, in particular, in high speed and low power applications. For example, PLL based circuits require a long acquisition time, normally in the range of 100-2000 cycles before a “lock” takes place. In high speed circuits, such delay is not acceptable. To minimize the acquisition time, one previous method maintained a certain level of transition activity as to maintain a PLL lock. However, such transition activity generally resulted in power dissipation which in certain instances is undesirable.
Accordingly, there is a need for an IEEE 1394-1995 compatible resync circuit that is suitable for high speed low power applications and that has a relatively short acquisition time.